Lateral short-channel dmos, method for manufacturing same and semiconductor device

ABSTRACT

A lateral short-channel DMOS  10 A according to the present invention includes an N − -type epitaxial layer  110  formed on a surface of a P − -type semiconductor substrate  108,  a P-type well  114  that is formed in a surface of the N − -type epitaxial layer  110  and includes a channel forming region C, an N + -type source region  116  formed in a surface of the P-type well  114,  an ON resistance lowering N-type well  134  formed in a surface of the N − -type epitaxial layer  110  so as to not contact the P-type well  114,  an N + -type drain region  118  formed in a surface of the ON resistance lowering N-type well  134,  a polysilicon gate electrode  122  formed via a gate insulating film  120  in at least an upper part of the channel forming region C out of a region from the N + -type source region  116  to the N + -type drain region  118,  and a gate resistance lowering metal layer  130  connected to the polysilicon gate electrode  122.    
     The lateral short-channel DMOS  10 A according to the present invention therefore has a low gate resistance and a low ON resistance, as well as superior high-speed switching characteristics and superior current driving characteristics.

TECHNICAL FIELD

[0001] The present invention relates to a lateral short-channel DMOSthat can be favorably used as a power MOSFET and a method ofmanufacturing the same. The present invention also relates to asemiconductor device equipped with this lateral short-channel DMOS.

RELATED ART

[0002]FIG. 13 is a cross-sectional view showing a conventional lateralshort-channel DMOS 90. As shown in FIG. 13, this lateral short-channelDMOS 90 includes an N⁻-type epitaxial layer 910 formed in a surface of aP⁻-type semiconductor substrate 908, a P-type well 914 that is formed ina surface of the N⁻-type epitaxial layer 910 and includes a channelforming region C, an N⁺-type source region 916 that is formed in asurface of the P-type well 914, an N⁺-type drain region 918 formed in asurface of the N⁻-type epitaxial layer 910, and a polysilicon gateelectrode 922 formed in an upper part of the channel forming region Cvia a gate insulating film 920 (see, for example, page 2 and FIG. 1 ofJapanese Laid-Open Patent Publication No. H08-213617 and FIG. 2.1 andpages 9 to 12 in “Pawaa MOSFET no Ouyou Gijutsu” (Power MOSFETApplications) by Hiroshi Yamazaki (First Edition, Eighth Impression)published on 23 Oct. 1998 by Nikkan Kougyou Shimbunsha).

[0003] In this lateral short-channel DMOS 90, the N⁺-type source region916 is connected to a source terminal, not shown, via a source electrode926, the N⁺-type drain region 918 is connected to a drain terminal, notshown, via a drain electrode 928, and a polysilicon gate electrode 922is connected to a gate terminal, not shown. The P⁻-type semiconductorsubstrate 908 is connected to ground 932 that is fixed at 0V.

[0004] However, this lateral short-channel DMOS 90 has had the problemthat high-speed switching is not easy due to the high resistance of thepolysilicon gate electrode.

[0005]FIG. 14 is a cross-sectional view of another conventional lateralshort-channel DMOS 92. As shown in FIG. 14, this lateral short-channelDMOS 92 is constructed so that a gate resistance lowering metal layer930 formed on an interlayer dielectric 924 is connected to thepolysilicon gate electrode 922. According to this lateral short-channelDMOS 92, since the gate resistance lowering metal layer 930 is connectedto the polysilicon gate electrode 922, the overall resistance of thegate electrode layer is lowered, so that high-speed switching ispossible.

[0006] However, in this lateral short-channel DMOS 92, a contact hole(A) needs to be provided in the interlayer dielectric 924 to connect thepolysilicon gate electrode 922 and the gate resistance lowering metallayer 930 and an isolation region (B) needs to be provided toelectrically isolate the gate resistance lowering metal layer 930 fromthe source electrode 926 and the drain electrode 928, so that the gatelength of the polysilicon gate electrode 922 becomes extended, resultingin the problem that the ON resistance is high.

[0007] The present invention was conceived in order to solve theproblems described above, and it is an object of the present inventionto provide a lateral short-channel DMOS with low gate resistance and alow ON resistance, as well as superior high-speed switchingcharacteristics and superior current driving characteristics. It is afurther object of the present invention to provide a method ofmanufacturing this superior lateral short-channel DMOS.

DISCLOSURE OF THE INVENTION

[0008] A lateral short-channel DMOS according to a first aspect of thepresent invention includes:

[0009] a first conductivity-type epitaxial layer formed on a surface ofa semiconductor substrate;

[0010] a second conductivity-type well that is formed in a surface ofthe first conductivity-type epitaxial layer and includes a channelforming region, the second conductivity type being an inverse of thefirst conductivity type;

[0011] a first conductivity-type source region that is formed in thesecond conductivity-type well;

[0012] a first conductivity-type ON resistance lowering well that isformed in the surface of the first conductivity-type epitaxial layer soas to not contact the second conductivity-type well and includes ahigher concentration of a first conductivity-type dopant than the firstconductivity-type epitaxial layer;

[0013] a first conductivity-type drain region formed in a surface of thefirst conductivity-type ON resistance lowering well;

[0014] a gate electrode formed, via a gate insulating film, in at leastan upper part of the channel forming region out of a region from thefirst conductivity-type source region to the first conductivity-typedrain region; and

[0015] a gate resistance lowering metal layer connected to the gateelectrode.

[0016] This means that according to the lateral short-channel DMOSaccording to the first aspect of the present invention, the firstconductivity-type ON resistance lowering well is formed in the surfaceof the first conductivity-type epitaxial layer so as to not contact thesecond conductivity-type well and the first conductivity-type drainregion is formed in a surface of the first conductivity-type ONresistance lowering well, so that when the DMOS is ON, the firstconductivity-type ON resistance lowering well that has low resistanceforms a large part of the current path between the firstconductivity-type source region and the first conductivity-type drainregion, therefore the overall ON resistance can be sufficiently loweredeven when the gate length is extended to lower the gate resistance.Accordingly, the lateral short-channel DMOS according to the firstaspect of the present invention has a low gate resistance and a low ONresistance, as well as superior high-speed switching characteristics andsuperior current driving characteristics.

[0017] Also, according to the lateral short-channel DMOS according tothe first aspect of the present invention, the first conductivity-typeON resistance lowering well that includes a higher concentration offirst conductivity-type dopant than the first conductivity-typeepitaxial layer is provided separately, so that it is possible to lowerthe ON resistance when the DMOS is ON without increasing theconcentration of dopant in the first conductivity-type epitaxial layeritself and therefore there is no decrease in the breakdowncharacteristics of the lateral short-channel DMOS.

[0018] For the lateral short-channel DMOS according to the first aspectof the present invention, the concentration of dopant in the firstconductivity-type ON resistance lowering well should preferably be atleast 1×10⁺¹⁸ ions/cm³ and the concentration of dopant in the firstconductivity-type epitaxial layer should preferably be no more than1×10⁺¹⁷ ions/cm³.

[0019] With the above construction, the resistance of the firstconductivity-type ON resistance lowering well can be sufficientlylowered and it is also possible to sufficiently maintain the breakdowncharacteristics of the lateral short-channel DMOS. In view of thispoint, the concentration of dopant in the first conductivity-type ONresistance lowering well should more preferably be at least 2×10⁺¹⁸ions/cm³, and even more preferably be at least 5×10⁺¹⁸ ions/cm³. Theconcentration of dopant in the first conductivity-type epitaxial layershould more preferably be no more than 5×10⁺¹⁶ ions/cm³, and even morepreferably be no more than 2×10⁺¹⁶ ions/cm³.

[0020] With the lateral short-channel DMOS according to the first aspectof the present invention, it is preferable that a secondconductivity-type diffused region is formed in a floating state in thesurface of the first conductivity-type epitaxial layer in a regionbetween the second conductivity-type well and the firstconductivity-type drain region so as to not contact the secondconductivity-type well.

[0021] With the above construction, it is possible to ease the electricfield strength during reverse bias in a vicinity of the region in whichthe second conductivity-type diffused region is formed, so that thebreakdown characteristics can be stabilized further. It should be notedthat when the DMOS is ON, the current between the firstconductivity-type drain region and the first conductivity-type sourceregion avoids the second conductivity-type dispersed region and flows ina deeper part (the first conductivity-type epitaxial layer) than thesecond conductivity-type diffused region, so that there is no increasein the ON resistance.

[0022] In view of this point, the concentration of dopant in the secondconductivity-type diffused region should preferably be in a range of3×10⁺¹⁶ ions/cm³ to 5×10⁺¹⁸ ions/cm³, and more preferably in a range of1×10⁺¹⁷ ions/cm³ to 1×10⁺¹⁸ ions/cm³.

[0023] With the lateral short-channel DMOS according to the first aspectof the present invention, it is preferable that the secondconductivity-type diffused region is formed so as to not contact thefirst conductivity-type ON resistance lowering well.

[0024] With the above construction, since the second conductivity-typediffused region that is not biased is constructed so as to not contactthe first conductivity-type ON resistance lowering well, it is possibleto thoroughly suppress a worsening of the breakdown characteristics andincreases in leak currents.

[0025] With the lateral short-channel DMOS according to the first aspectof the present invention, it is preferable that in a region from thesecond conductivity-type diffused region to the first conductivity-typedrain region, the gate electrode is provided opposite the firstconductivity-type epitaxial layer with a field oxide film in between.

[0026] With the above construction, the electric field strength duringreverse bias in a vicinity of the region in which the secondconductivity-type diffused region is formed is eased, so that it ispossible to increase the thickness of the gate insulating film in aregion from the second conductivity-type diffused region to the firstconductivity-type drain region. This means that it is possible to use aconstruction where the gate electrode is provided opposite the firstconductivity-type epitaxial layer with the field oxide film in between,and as a result, a capacity between the gate and the source and betweenthe gate and the drain can be reduced, thereby making it possible tofurther improve the high-speed switching characteristics.

[0027] A lateral short-channel DMOS according to a second aspect of thepresent invention includes:

[0028] an epitaxial layer formed on a surface of a semiconductorsubstrate;

[0029] a first conductivity-type well formed in a surface of theepitaxial layer;

[0030] a second conductivity-type well that is formed in a surface ofthe first conductivity-type well and includes a channel forming region,the second conductivity type being an inverse of the first conductivitytype;

[0031] a first conductivity-type source region that is formed in asurface of the second conductivity-type well;

[0032] a first conductivity-type ON resistance lowering well that isformed in a surface of the epitaxial layer so as to contact the firstconductivity-type well and to not contact the second conductivity-typewell, and includes a higher concentration of a first conductivity-typedopant than the first conductivity-type well;

[0033] a first conductivity-type drain region formed in a surface of thefirst conductivity-type ON resistance lowering well;

[0034] a gate electrode formed, via a gate insulating film, in an upperpart of at least the channel forming region out of a region from thefirst conductivity-type source region to the first conductivity-typedrain region; and

[0035] a gate resistance lowering metal layer connected to the gateelectrode.

[0036] This means that according to the lateral short-channel DMOSaccording to the second aspect of the present invention, the firstconductivity-type ON resistance lowering well is formed in the surfaceof the epitaxial layer so as to not contact the second conductivity-typewell and the first conductivity-type drain region is formed in a surfaceof the first conductivity-type ON resistance lowering well, so that whenthe DMOS is ON, the first conductivity-type ON resistance lowering wellthat has low resistance forms a large part of the current path betweenthe first conductivity-type source region and the firstconductivity-type drain region, therefore the overall ON resistance canbe sufficiently lowered even when the gate length is extended to lowerthe gate resistance. Accordingly, the lateral short-channel DMOSaccording to the second aspect of the present invention has a low gateresistance and a low ON resistance, as well as superior high-speedswitching characteristics and superior current driving characteristics.

[0037] Also, according to the lateral short-channel DMOS according tothe second aspect of the present invention, the first conductivity-typeON resistance lowering well that includes a higher concentration offirst conductivity-type dopant than the first conductivity-type well isprovided separately, so that it is possible to lower the resistance whenthe DMOS is ON without increasing the concentration of dopant in thefirst conductivity-type well and therefore there is no decrease in thebreakdown characteristics of the lateral short-channel DMOS.

[0038] In addition, in a semiconductor device where this lateralshort-channel DMOS has been integrated with other elements (such aslogic elements), since the first conductivity-type well is formed insidethe epitaxial layer, it is possible to control the breakdowncharacteristics of the lateral short-channel DMOS via the concentrationof dopant in the first conductivity-type well, so that the concentrationof dopant in the epitaxial layer can be set at an appropriateconcentration (for example, a lower concentration than the firstconductivity-type well) for the other elements (such as logic elements),therefore a semiconductor device with more superior characteristics canbe provided.

[0039] For the lateral short-channel DMOS according to the second aspectof the present invention, the concentration of dopant in the firstconductivity-type ON resistance lowering well should preferably be atleast 1×10⁺¹⁸ ions/cm³ and the concentration of dopant in the firstconductivity-type well should preferably be no more than 1×10⁺¹⁷ions/cm³.

[0040] With the above construction, the resistance of the firstconductivity-type ON resistance lowering well can be sufficientlylowered and it is also possible to sufficiently maintain the breakdowncharacteristics of the lateral short-channel DMOS. In view of thispoint, the concentration of dopant in the first conductivity-type ONresistance lowering well should more preferably be at least 2×10⁺¹⁸ions/cm³, and even more preferably be at least 5×10⁺¹⁸ ions/cm³. Theconcentration of dopant in the first conductivity-type well should morepreferably be no more than 5×10⁺¹⁶ ions/cm³, and even more preferably beno more than 2×10⁺¹⁶ ions/cm³.

[0041] With the lateral short-channel DMOS according to the secondaspect of the present invention, it is preferable that a secondconductivity-type diffused region is formed in a floating state in thesurface of the first conductivity-type well in a region between thesecond conductivity-type well and the first conductivity-type drainregion so as to not contact the second conductivity-type well.

[0042] With the above construction, it is possible to ease the electricfield strength during reverse bias in a vicinity of the region in whichthe second conductivity-type diffused region is formed, so that thebreakdown characteristics can be stabilized further. It should be notedthat when the DMOS is ON, the current between the firstconductivity-type drain region and the first conductivity-type sourceregion avoids the second conductivity-type diffused region and flows ina deeper part (the first conductivity-type well) than the secondconductivity-type diffused region, so that there is no increase in theON resistance.

[0043] In view of this point, the concentration of dopant in the secondconductivity-type diffused region should preferably be in a range of3×10⁺¹⁶ ions/cm³ to 5×10⁺¹⁸ ions/cm³, and more preferably in a range of1×10⁺¹⁷ ions/cm³ to 1×10⁺¹⁸ ions/cm³.

[0044] With the lateral short-channel DMOS according to the secondaspect of the present invention, it is preferable that the secondconductivity-type diffused region is formed so as to not contact thefirst conductivity-type ON resistance lowering well.

[0045] With the above construction, since the second conductivity-typediffused region that is not biased is constructed so as to not contactthe first conductivity-type ON resistance lowering well, it is possibleto thoroughly suppress a worsening of the breakdown characteristics andincreases in leak currents.

[0046] With the lateral short-channel DMOS according to the secondaspect of the present invention, it is preferable that in a region fromthe second conductivity-type diffused region to the firstconductivity-type drain region, the gate electrode is provided oppositethe epitaxial layer with a field oxide film in between.

[0047] With the above construction, the electric field strength duringreverse bias in a vicinity of the region in which the secondconductivity-type diffused region is formed is eased, so that it ispossible to increase the thickness of the gate insulating film in aregion from the second conductivity-type diffused region to the firstconductivity-type drain region. This means that it is possible to use aconstruction where the gate electrode is provided opposite the epitaxiallayer with the field oxide film in between, and as a result, a capacitybetween the gate and the source and between the gate and the drain canbe reduced, thereby making it possible to further improve the high-speedswitching characteristics.

[0048] A lateral short-channel DMOS according to a third aspect of thepresent invention includes:

[0049] a first conductivity-type well formed in a surface of asemiconductor substrate;

[0050] a second conductivity-type well that is formed in a surface ofthe first conductivity-type well and includes a channel forming region,the second conductivity type being an inverse of the first conductivitytype;

[0051] a first conductivity-type source region that is formed in asurface of the second conductivity-type well;

[0052] a first conductivity-type ON resistance lowering well that isformed in a surface of the semiconductor substrate so as to contact thefirst conductivity-type well and not contact the secondconductivity-type well, and includes a higher concentration of a firstconductivity-type dopant than the first conductivity-type well;

[0053] a first conductivity-type drain region formed in a surface of thefirst conductivity-type ON resistance lowering well;

[0054] a gate electrode formed, via a gate insulating film, in an upperpart of at least the channel forming region out of a region from thefirst conductivity-type source region to the first conductivity-typedrain region; and

[0055] a gate resistance lowering metal layer connected to the gateelectrode.

[0056] This means that according to the lateral short-channel DMOSaccording to the third aspect of the present invention, the firstconductivity-type ON resistance lowering well is formed in the surfaceof the semiconductor substrate so as to contact the firstconductivity-type well and not contact the second conductivity-type welland the first conductivity-type drain region is formed in a surface ofthe first conductivity-type ON resistance lowering well, so that whenthe DMOS is ON, the first conductivity-type ON resistance lowering wellthat has low resistance forms a large part of the current path betweenthe first conductivity-type source region and the firstconductivity-type drain region, therefore the overall ON resistance canbe sufficiently lowered even when the gate length is extended to lowerthe gate resistance. Accordingly, the lateral short-channel DMOSaccording to the third aspect of the present invention has a low gateresistance and a low ON resistance, as well as superior high-speedswitching characteristics and superior current driving characteristics.

[0057] Also, according to the lateral short-channel DMOS according tothe third aspect of the present invention, the first conductivity-typeON resistance lowering well that includes a higher concentration offirst conductivity-type dopant than the first conductivity-type well isprovided separately, so that it is possible to lower the ON resistancewhen the DMOS is ON without increasing the concentration of dopant inthe first conductivity-type well and therefore there is no decrease inthe breakdown characteristics of the lateral short-channel DMOS.

[0058] In addition, although the first conductivity-type well needs tobe formed relatively deeply from the surface of the semiconductorsubstrate in order to maintain the breakdown characteristics of thelateral short-channel DMOS, the first conductivity-type ON resistancelowering well only needs to act as a current path from the firstconductivity-type drain region to the first conductivity-type sourceregion and so may be formed relatively shallowly from the surface of thesemiconductor substrate. This means that little extension in thehorizontal direction is required when forming the firstconductivity-type ON resistance lowering well, and as a result, theelement area of the lateral short-channel DMOS does not becomeparticularly large.

[0059] Also, since a first conductivity-type ON resistance lowering wellis formed, the length is suppressed for a depletion layer formed with alarge width from a PN junction formed by the second conductivity-typewell and the first conductivity-type well during reverse bias towardsthe first conductivity-type drain region, resulting in the effect thatthe breakdown characteristics can be stabilized without the electricfield strength at the surface of the semiconductor substrate becominglarge.

[0060] For the lateral short-channel DMOS according to the third aspectof the present invention, the concentration of dopant in the firstconductivity-type ON resistance lowering well should preferably be atleast 1×10⁺¹⁸ ions/cm³ and the concentration of dopant in the firstconductivity-type well should preferably be no more than 1×10⁺¹⁷ions/cm³.

[0061] With the above construction, the resistance of the firstconductivity-type ON resistance lowering well can be sufficientlylowered and it is also possible to sufficiently maintain the breakdowncharacteristics of the lateral short-channel DMOS. In view of thispoint, the concentration of dopant in the first conductivity-type ONresistance lowering well should more preferably be at least 2×10⁺¹⁸ions/cm³, and even more preferably be at least 5×10⁺¹⁸ ions/cm³. Theconcentration of dopant in the first conductivity-type well should morepreferably be no more than 5×10⁺¹⁶ ions/cm³, and even more preferably beno more than 2×10⁺¹⁶ ions/cm³.

[0062] With the lateral short-channel DMOS according to the third aspectof the present invention, it is preferable that a secondconductivity-type diffused region is formed in a floating state in thesurface of the first conductivity-type well in a region between thesecond conductivity-type well and the first conductivity-type drainregion so as to not contact the second conductivity-type well.

[0063] With the above construction, it is possible to ease the electricfield strength during reverse bias in a vicinity of the region in whichthe second conductivity-type diffused region is formed, so that thebreakdown characteristics can be stabilized further. It should be notedthat when the DMOS is ON, the current between the firstconductivity-type drain region and the first conductivity-type sourceregion avoids the second conductivity-type diffused region and flows ina deeper part (the first conductivity-type well) than the secondconductivity-type diffused region, so that there is no increase in theON resistance.

[0064] In view of this point, the concentration of dopant in the secondconductivity-type diffused region should preferably be in a range of3×10⁺¹⁶ ions/cm³ to 5×10⁺¹⁸ ions/cm³, and more preferably in a range of1×10⁺¹⁷ ions/cm³ to 1×10⁺¹⁸ ions/cm³.

[0065] With the lateral short-channel DMOS according to the third aspectof the present invention, it is preferable that the secondconductivity-type diffused region is formed so as to not contact thefirst conductivity-type ON resistance lowering well.

[0066] With the above construction, since the second conductivity-typediffused region that is not biased is constructed so as to not contactthe first conductivity-type ON resistance lowering well, it is possibleto thoroughly suppress a worsening of the breakdown characteristics andincreases in leak currents.

[0067] With the lateral short-channel DMOS according to the third aspectof the present invention, it is preferable that in a region from thesecond conductivity-type diffused region to the first conductivity-typedrain region, the gate electrode is provided opposite the semiconductorsubstrate with a field oxide film in between.

[0068] With the above construction, the electric field strength duringreverse bias in a vicinity of the region in which the secondconductivity-type diffused region is formed is eased, so that it ispossible to increase the thickness of the gate insulating film in aregion from the second conductivity-type diffused region to the firstconductivity-type drain region. This means that it is possible to use aconstruction where the gate electrode is provided opposite thesemiconductor substrate with the field oxide film in between, and as aresult, a capacity between the gate and the source and between the gateand the drain can be reduced, thereby making it possible to furtherimprove the high-speed switching characteristics.

[0069] As described above, as should be dear from the lateralshort-channel DMOS according to the first to third aspects, in thelateral short-channel DMOS according to the present invention thecurrent that flows between the first conductivity-type source region,which is formed in the surface of the second conductivity-type well thatincludes the channel forming region, and the first conductivity-typedrain region can be controlled by a voltage applied to the gateelectrode formed via the gate insulating film in an upper part of atleast the channel forming region out of a region from the firstconductivity-type source region to the first conductivity-type drainregion, where the first conductivity-type drain region is formed in thesurface of the first conductivity-type ON resistance lowering well thatis formed so as to not contact the second conductivity-type well.

[0070] In the lateral short-channel DMOS according to the first to thirdaspects of the present invention, silicon can be favorably used as thesemiconductor substrate. Polysilicon, tungsten silicide, molybdenumsilicide, tungsten, molybdenum, copper, aluminum, and the like can befavorably used as the material of the gate electrode. Also, tungsten,molybdenum, copper, aluminum, and the like can be favorably used as thegate electrode resistance lowering metal.

[0071] It should be noted that in the lateral short-channel DMOSaccording to the present invention, it is possible to set the secondconductivity-type at P-type and the first conductivity-type at N-type orto set the second conductivity-type at N-type and the firstconductivity-type at P-type.

[0072] A “method of manufacturing a lateral short-channel DMOS”according to a first aspect of the present invention is a method ofmanufacturing “the lateral short-channel DMOS” according to the firstaspect of the present invention and includes the following steps inorder:

[0073] (a) a first step of preparing the semiconductor substrate withthe first conductivity-type epitaxial layer formed on the surfacethereof;

[0074] (b) a second step of forming a first ion implanting mask with apredetermined opening on a surface of the first conductivity-typeepitaxial layer and forming the first conductivity-type ON resistancelowering well by implanting first conductivity-type dopant with thefirst ion implanting mask as a mask;

[0075] (c) a third step of forming, after removal of the first ionimplanting mask, a second ion implanting mask with a predeterminedopening on the surface of the first conductivity-type epitaxial layerand forming the second conductivity-type well so as to not contact thefirst conductivity-type ON resistance lowering well by implanting secondconductivity-type dopant with the second ion implanting mask as a mask;

[0076] (d) a fourth step of forming, after removal of the second ionimplanting mask, a field oxide film with a predetermined opening in thesurface of the first conductivity-type epitaxial layer and forming thegate insulating film by thermal oxidization at the opening in the fieldoxide film;

[0077] (e) a fifth step of forming the gate electrode in a predeterminedregion on the gate insulating film; and

[0078] (f) a sixth step of forming the first conductivity-type sourceregion and the first conductivity-type drain region by implanting firstconductivity-type dopant with at least the gate electrode and the fieldoxide film as a mask.

[0079] This means that the superior “lateral short-channel DMOS”according to the first aspect of the present invention can be obtainedby the “method of manufacturing a lateral short-channel DMOS” accordingto the first aspect of the present invention.

[0080] A “method of manufacturing a lateral short-channel DMOS”according to a second aspect of the present invention is a method ofmanufacturing “the lateral short-channel DMOS” according to the secondaspect of the present invention and includes the following steps inorder:

[0081] (a) a first step of preparing the semiconductor substrate withthe epitaxial layer formed on the surface thereof;

[0082] (b) a second step of forming a first ion implanting mask with apredetermined opening on a surface of the epitaxial layer and formingthe first conductivity-type well by implanting first conductivity-typedopant into the semiconductor substrate with the first ion implantingmask as a mask;

[0083] (c) a third step of forming, after removal of the first ionimplanting mask, a second ion implanting mask with a predeterminedopening on the surface of the epitaxial layer and forming the firstconductivity-type ON resistance lowering well so as to contact the firstconductivity-type well by implanting first conductivity-type dopant witha higher concentration than the second step with the second ionimplanting mask as a mask;

[0084] (d) a fourth step of forming, after removal of the second ionimplanting mask, a third ion implanting mask with a predeterminedopening on the surface of the epitaxial layer and forming the secondconductivity-type well so as to not contact the first conductivity-typeON resistance well by implanting second conductivity-type dopant withthe third ion implanting mask as a mask;

[0085] (e) a fifth step of forming, after removal of the third ionimplanting mask, a field oxide film with a predetermined opening in thesurface of the epitaxial layer and forming the gate insulating film bythermal oxidization at the opening in the field oxide film;

[0086] (f) a sixth step of forming the gate electrode in a predeterminedregion on the gate insulating film; and

[0087] (g) a seventh step of forming the first conductivity-type sourceregion and the first conductivity-type drain region by implanting firstconductivity-type dopant with at least the gate electrode and the fieldoxide film as a mask.

[0088] This means that the superior “lateral short-channel DMOS”according to the second aspect of the present invention can be obtainedby the “method of manufacturing a lateral short-channel DMOS” accordingto the second aspect of the present invention.

[0089] A “method of manufacturing a lateral short-channel DMOS”according to a third aspect of the present invention is a method ofmanufacturing “the lateral short-channel DMOS” according to the thirdaspect of the present invention and includes the following steps inorder:

[0090] (a) a first step of preparing a semiconductor substrate;

[0091] (b) a second step of forming a first ion implanting mask with apredetermined opening on a surface of the semiconductor substrate andforming the first conductivity-type well by implanting firstconductivity-type dopant into the semiconductor substrate with the firstion implanting mask as a mask;

[0092] (c) a third step of forming, after removal of the first ionimplanting mask, a second ion implanting mask with a predeterminedopening on a surface of the semiconductor substrate and forming thefirst conductivity-type ON resistance lowering well so as to contact thefirst conductivity-type well by implanting first conductivity-typedopant with a higher concentration than the second step with the secondion implanting mask as a mask;

[0093] (d) a fourth step of forming, after removal of the second ionimplanting mask, a third ion implanting mask with a predeterminedopening on a surface of the semiconductor substrate and forming thesecond conductivity-type well so as to not contact the firstconductivity-type ON resistance well by implanting secondconductivity-type dopant with the third ion implanting mask as a mask;

[0094] (e) a fifth step of forming, after removal of the third ionimplanting mask, a field oxide film with a predetermined opening in asurface of the semiconductor substrate, and forming the gate insulatingfilm by thermal oxidization at the opening in the field oxide film;

[0095] (f) a sixth step of forming the gate electrode in a predeterminedregion on the gate insulating film; and

[0096] (g) a seventh step of forming the first conductivity-type sourceregion and the first conductivity-type drain region by implanting firstconductivity-type dopant with at least the gate electrode and the fieldoxide film as a mask.

[0097] This means that the superior “lateral short-channel DMOS”according to the third aspect of the present invention can be obtainedby the “method of manufacturing a lateral short-channel DMOS” accordingto the third aspect of the present invention.

[0098] The semiconductor device according to the present inventionincludes a lateral short-channel DMOS according to any of the first tothird aspects.

[0099] The semiconductor device according to the present invention is asuperior power control semiconductor device since it includes a lateralshort-channel DMOS with low gate resistance and low ON resistance aswell as superior high-speed switching characteristics and currentdriving characteristics.

[0100] The semiconductor device according to the present invention canalso include logic circuits. By using this construction, thesemiconductor device according to the present invention is a superiorpower control semiconductor device since it includes a lateralshort-channel DMOS with low gate resistance and low ON resistance aswell as superior high-speed switching characteristics and currentdriving characteristics, as well as logic circuits for controlling thelateral short-channel DMOS.

[0101] In the semiconductor device according to the present invention,it is preferable to use the lateral short-channel DMOS according to thesecond aspect described above as the lateral short-channel DMOS. Whenthis construction is used, a lateral short-channel DMOS in which thefirst conductivity-type well is formed inside the epitaxial layer isused, so that the breakdown characteristics of the lateral short-channelDMOS can be controlled via the concentration of dopant in the firstconductivity-type well. As a result, the concentration of dopant in theepitaxial layer can be set at a concentration suited to the logiccircuits (for example, a lower concentration than the firstconductivity-type well), so that a power control semiconductor devicewith superior characteristics can be produced.

BRIEF DESCRIPTION OF THE DRAWINGS

[0102]FIG. 1A is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 1A.

[0103]FIG. 1B is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 1B.

[0104]FIG. 1C is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 1C.

[0105]FIG. 1D is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 1D.

[0106]FIG. 1E is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 1E.

[0107]FIG. 2A is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 2A.

[0108]FIG. 2B is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 2B.

[0109]FIG. 2C is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 2C.

[0110]FIG. 2D is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 2D.

[0111]FIG. 2E is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 2E.

[0112]FIG. 2F is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 2F.

[0113]FIG. 3A is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 3A.

[0114]FIG. 3B is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 3B.

[0115]FIG. 3C is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 3C.

[0116]FIG. 3D is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 3D.

[0117]FIG. 3E is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 3E.

[0118]FIG. 4A is a plan view of a lateral short-channel DMOS accordingto embodiment 3D.

[0119]FIG. 4B is a plan view of a lateral short-channel DMOS accordingto embodiment 3D.

[0120]FIG. 5 is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 3D.

[0121]FIG. 6 is a cross-sectional view of a semiconductor device inwhich a lateral short-channel DMOS according to embodiment 2E has beenintegrated with other elements.

[0122]FIGS. 7a to 7 f are diagrams showing manufacturing processes for alateral short-channel DMOS according to embodiment 4.

[0123]FIGS. 8a to 8 g are diagrams showing manufacturing processes for alateral short-channel DMOS according to embodiment 5.

[0124]FIGS. 9a to 9 g are diagrams showing manufacturing processes for alateral short-channel DMOS according to embodiment 6.

[0125]FIG. 10 is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 7E.

[0126]FIG. 11A is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 8E.

[0127]FIG. 11B is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 8F.

[0128]FIG. 12 is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 9E.

[0129]FIG. 13 is a cross-sectional view of a conventional lateralshort-channel DMOS.

[0130]FIG. 14 is a cross-sectional view of a conventional lateralshort-channel DMOS.

BEST MODE FOR CARRYING OUT THE PRESENT INVENTION

[0131] Embodiments of the present invention are described in detailbelow with reference to the attached drawings.

[0132] Embodiment 1A

[0133]FIG. 1A is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 1A of the present invention. A lateralshort-channel DMOS 10A according to this embodiment 1A is a lateralshort-channel DMOS according to a first aspect of the present invention,and as shown in FIG. 1A, has an N⁻-type epitaxial layer (firstconductivity-type epitaxial layer) 110 formed on a surface of a P⁻-typesemiconductor substrate (semiconductor substrate) 108. A P-type well(second conductivity-type well) 114 including a channel forming region Cis formed in a surface of the N⁻-type epitaxial layer 110, and anN⁺-type source region (first conductivity-type source region) 116 isformed in a surface of the P-type well 114. On the other hand, an ONresistance lowering N-type well (first conductivity-type ON resistancelowering well) 134 is formed in a surface of the N⁻-type epitaxial layer110 so as to not contact the P-type well 114. An N⁺-type drain region(first conductivity-type drain region) 118 is formed in a surface ofthis ON resistance lowering N-type well 134.

[0134] A polysilicon gate electrode 122 is formed via a gate insulatingfilm 120 in at least an upper part of the channel forming region C, outof a region from the N⁺-type source region 116 to the N⁺-type drainregion 118. The polysilicon gate electrode 122 is connected to a gateresistance lowering metal layer 130. An element isolating region 140 isalso formed on a right side of the N⁺-type drain region 118.

[0135] This means that according to the lateral short-channel DMOS 10Aaccording to embodiment 1A, the ON resistance lowering N-type well 134is formed in the N⁻-type epitaxial layer 110 so as to not contact theP-type well 114 and the N⁺-type drain region 118 is formed in thesurface of the ON resistance lowering N-type well 134, so that when theDMOS 10A is ON, the ON resistance lowering N-type well 134 that has lowresistance forms a large part of the current path from the N⁺-type drainregion 118 to the N⁺-type source region 116 and the overall ONresistance can be sufficiently lowered even when the gate length isextended to lower the gate resistance. Accordingly, the lateralshort-channel DMOS 10A according to embodiment 1A has a low gateresistance and a low ON resistance, as well as superior high-speedswitching characteristics and superior current driving characteristics.

[0136] Also, according to the lateral short-channel DMOS 10A accordingto embodiment 1A, the ON resistance lowering N-type well 134 thatincludes a higher concentration of N-type dopant than the N⁻-typeepitaxial layer 110 is provided separately, so that the resistance whenthe DMOS 10A is ON can be lowered without increasing the concentrationof dopant in the N⁻-type epitaxial layer 110 itself and there is noworsening in the breakdown characteristics of the lateral short-channelDMOS.

[0137] In the lateral short-channel DMOS 10A according to embodiment 1A,the depth of the P-type well 114 is 1.5 μm, for example, the depth ofthe N⁺-type source region 116 is 0.3 μm, for example, the depth of theN⁺-type drain region 118 is 0.3 μm, for example, and the depth of the ONresistance lowering N-type well 134 is 2 μm, for example.

[0138] In the lateral short-channel DMOS 10A according to embodiment 1A,the dopant concentration of the ON resistance lowering N-type well 134is 1×10⁺¹⁹ ions/cm³, for example, and the dopant concentration of theN⁻-type epitaxial layer 110 is 1×10⁺¹⁶ ions/cm³, for example.

[0139] Embodiment 1B

[0140]FIG. 1B is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 1B. A lateral short-channel DMOS 10B accordingto embodiment 1B has a similar structure to the lateral short-channelDMOS 10A according to embodiment 1A, but as shown in FIG. 1B, thedifference is that a P-type diffused region (second conductivity-typediffused region) 138 is formed in a floating state in a region betweenthe P-type well 114 and the N⁺-type drain region 118 in a surface of theN⁻-type epitaxial layer 110 so as to not contact the P-type well 114.

[0141] According to the lateral short-channel DMOS 10B according toembodiment 1B, the following effect is obtained in addition to theeffects of the lateral short-channel DMOS 10A according to embodiment1A. That is, an electric field strength in the region in which theP-type diffused region 138 is formed is eased during reverse bias, sothat the breakdown characteristics can be stabilized further.

[0142] It should be noted that when the DMOS 10B is ON, the current fromthe N⁺-type drain region 118 to the N⁺-type source region 116 avoids theP-type diffused region 138 and flows in a deeper part (the N⁻-typeepitaxial layer 110) than the P-type diffused region 138, so that thereis no increase in the ON resistance due to the provision of the P-typediffused region 138.

[0143] In the lateral short-channel DMOS 10B according to embodiment 1B,the dopant concentration of the P-type diffused region 138 is 3×10⁺¹⁷ions/cm³, for example.

[0144] Embodiment 1C

[0145]FIG. 1C is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 1C. A lateral short-channel DMOS 10C accordingto embodiment 1C has a similar construction to the lateral short-channelDMOS 10B according to embodiment 1B, with the difference being that theP-type diffused region 138 is formed so as to not contact the ONresistance lowering N-type well 134.

[0146] This means that in addition to the effects of the lateralshort-channel DMOS 10B according to embodiment 1B, the lateralshort-channel DMOS 10C according to embodiment 1C has the followingeffect. That is, since the P-type diffused region 138 that is not biasedis constructed so as to not contact the ON resistance lowering N-typewell 134, it is possible to thoroughly suppress a worsening of thebreakdown characteristics and increases in leak currents.

[0147] Embodiment 1D

[0148]FIG. 1D is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 1D. A lateral short-channel DMOS 10D accordingto embodiment 1D has a similar construction to the lateral short-channelDMOS 10B according to embodiment 1B, with as shown in FIG. 1D, thedifference being that in a region from the P-type diffused region 138 tothe N⁺-type drain region 118, the polysilicon gate electrode 122 isprovided opposite the N⁻-type epitaxial layer 110 with a field oxidefilm 136 in between.

[0149] This means that in addition to the effects of the lateralshort-channel DMOS 10B according to embodiment 1B, the lateralshort-channel DMOS 10D according to embodiment 1D has the followingeffect. That is, the capacity between the gate and the source andbetween the gate and the drain can be reduced, so that the high-speedswitching characteristics can be further improved. This is because theelectric field strength during reverse bias is eased in a vicinity of aregion in which the P-type diffused region 138 is formed, so that it ispossible to use a construction where in a region from the P-typediffused region 138 to the N⁺-type drain region 118, the polysilicongate electrode 122 is provided opposite the N⁻-type epitaxial layer 110with a thick field oxide film 136 in between.

[0150] Embodiment 1E

[0151]FIG. 1E is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 1E. A lateral short-channel DMOS 10E accordingto embodiment 1E has a similar construction to the lateral short-channelDMOS 10C according to embodiment 1C, with as shown in FIG. 1E, thedifference being that in a region from the P-type diffused region 138 tothe N⁺-type drain region 118, the polysilicon gate electrode 122 isprovided opposite the N⁻-type epitaxial layer 110 with the field oxidefilm 136 in between.

[0152] This means that in addition to the effects of the lateralshort-channel DMOS 10C according to embodiment 1C, the lateralshort-channel DMOS 10E according to embodiment 1E has the followingeffect. That is, the capacity between the gate and the source andbetween the gate and the drain can be reduced, so that the high-speedswitching characteristics can be further improved. This is because theelectric field strength during reverse bias is eased in a vicinity of aregion in which the P-type diffused region 138 is formed, so that it ispossible to use a construction where in a region from the P-typediffused region 138 to the N⁺-type drain region 118, the polysilicongate electrode 122 is provided opposite the N⁻-type epitaxial layer 110with a thick field oxide film 136 in between.

[0153] Embodiment 2A

[0154]FIG. 2A is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 2A of the present invention. A lateralshort-channel DMOS 20A according to this embodiment 2A is a lateralshort-channel DMOS according to a second aspect of the presentinvention, and as shown in FIG. 2A, has an N⁻-type epitaxial layer(epitaxial layer) 210 formed on a surface of a P⁻-type semiconductorsubstrate (semiconductor substrate) 208, and an N⁻-type well (firstconductivity-type well) 212 formed in a surface of the N⁻-type epitaxiallayer 210. A P-type well (second conductivity-type well) 214 including achannel forming region C is formed in a surface of the N⁻-type well 212,and an N⁺-type source region (first conductivity-type source region) 216is formed in a surface of the P-type well 214. On the other hand, an ONresistance lowering N-type well (first conductivity-type ON resistancelowering well) 234 is formed in a surface of the N⁻-type epitaxial layer210 so as to not contact the P-type well 214, and an N⁺-type drainregion (first conductivity-type drain region) 218 is formed in a surfaceof the ON resistance lowering N-type well 234.

[0155] A polysilicon gate electrode 222 is formed via a gate insulatingfilm 220 in at least an upper part of the channel forming region C, outof a region from the N⁺-type source region 216 to the N⁺-type drainregion 218. The polysilicon gate electrode 222 is connected to a gateresistance lowering metal layer 230. An element isolating region 240 isalso formed on a right side of the N⁺-type drain region 218.

[0156] This means that according to the lateral short-channel DMOS 20Aaccording to embodiment 2A, the ON resistance lowering N-type well 234is formed in the surface of the N⁻-type epitaxial layer 210 so as to notcontact the P-type well 214 and the N⁺-type drain region 218 is formedin the surface of the ON resistance lowering N-type well 234, so thatwhen the DMOS 20A is ON, the ON resistance lowering N-type well 234 thathas low resistance provides a large part of the current path from theN⁺-type drain region 218 to the N⁺-type source region 216 and theoverall ON resistance can be sufficiently lowered even when the gatelength is extended to lower the gate resistance. Accordingly, thelateral short-channel DMOS 20A according to embodiment 2A has a low gateresistance and a low ON resistance, as well as superior high-speedswitching characteristics and superior current driving characteristics.

[0157] Also, according to the lateral short-channel DMOS 20A accordingto embodiment 2A, the ON resistance lowering N-type well 234 thatincludes a higher concentration of N-type dopant than the N⁻-type well212 is provided separately, so that the resistance when the DMOS 20A isON can be lowered without increasing the concentration of dopant in theN⁻-type well 212 and there is no worsening in the breakdowncharacteristics of the lateral short-channel DMOS.

[0158] Also, according to the lateral short-channel DMOS 20A accordingto embodiment 2A, the N⁻-type well 212 is formed inside the N⁻-typeepitaxial layer 210, so that even in a semiconductor device where alateral short-channel DMOS is integrated with other elements (such as alogic element), the breakdown characteristics of the lateralshort-channel DMOS can be controlled according to the dopantconcentration of the N⁻-type well 212. As a result, it is possible toset the dopant concentration of the N⁻-type epitaxial layer 210 at anappropriate concentration for other elements (such as a lowerconcentration than the N⁻-type well 212), so that a semiconductor devicewith superior characteristics can be provided.

[0159] In the lateral short-channel DMOS 20A according to embodiment 2A,the depth of the N⁻-type well 212 is 5 μm, for example, the depth of theP-type well 214 is 1.5 μm, for example, the depth of the N⁺-type sourceregion 216 is 0.3 μm, for example, the depth of the N⁺-type drain region218 is 0.3 μm, for example, and the depth of the ON resistance loweringN-type well 234 is 2 μm, for example.

[0160] In the lateral short-channel DMOS 20A according to embodiment 2A,the dopant concentration of the ON resistance lowering N-type well 234is 1×10⁺¹⁹ ions/cm³, for example, the dopant concentration of theN⁻-type epitaxial layer 210 is 5×10⁺¹⁵ ions/cm³, for example, and thedopant concentration of the N⁻-type well 212 is 1×10⁺¹⁶ ions/cm³, forexample.

[0161] Embodiment 2B

[0162]FIG. 2B is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 2B. A lateral short-channel DMOS 20B accordingto embodiment 2B has a similar structure to the lateral short-channelDMOS 20A according to embodiment 2A, with as shown in FIG. 2B, thedifference being that a P-type diffused region (second conductivity-typediffused region) 238 is formed in a region between the P-type well 214and the N⁺-type drain region 218 in a surface of the N⁻-type well 212 soas to not contact the P-type well 214.

[0163] According to the lateral short-channel DMOS 20B according toembodiment 2B, the following effect is obtained in addition to theeffects of the lateral short-channel DMOS 20A according to embodiment2A. That is, an electric field strength in a vicinity of the region inwhich the P-type diffused region 238 is formed is eased duringapplication of reverse bias, so that the breakdown characteristics canbe stabilized further.

[0164] It should be noted that when the DMOS 20B is ON, the current fromthe N⁺-type drain region 218 to the N⁺-type source region 216 avoids theP-type diffused region 238 and flows in a deeper part (the N⁻-type well212) than the P-type diffused region 238, so that there is no increasein the ON resistance due to the provision of the P-type diffused region238.

[0165] In the lateral short-channel DMOS 20B according to embodiment 2B,the dopant concentration of the P-type diffused region 238 is 3×10⁺¹⁷ions/cm³, for example.

[0166] Embodiment 2C

[0167]FIG. 2C is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 2C. A lateral short-channel DMOS 20C accordingto embodiment 2C has a similar construction to the lateral short-channelDMOS 20B according to embodiment 2B, with the difference being that theP-type diffused region 238 is formed so as to not contact the ONresistance lowering N-type well 234.

[0168] This means that in addition to the effects of the lateralshort-channel DMOS 20B according to embodiment 2B, the lateralshort-channel DMOS 20C according to embodiment 2C has the followingeffect. That is, since the P-type diffused region 238 that is not biasedis constructed so as to not contact the ON resistance lowering N-typewell 234, it is possible to thoroughly suppress a worsening of thebreakdown characteristics and increases in leak currents.

[0169] Embodiment 2D

[0170]FIG. 2D is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 2D. A lateral short-channel DMOS 20D accordingto embodiment 2D has a similar construction to the lateral short-channelDMOS 20B according to embodiment 2B, with as shown in FIG. 2D, thedifference being that in a region from the P-type diffused region 238 tothe N⁺-type drain region 218, the polysilicon gate electrode 222 isprovided opposite the N⁻-type epitaxial layer 210 with a field oxidefilm 236 in between.

[0171] This means that in addition to the effects of the lateralshort-channel DMOS 20B according to embodiment 2B, the lateralshort-channel DMOS 20D according to embodiment 2D has the followingeffect. That is, the capacity between the gate and the source andbetween the gate and the drain can be reduced, so that the high-speedswitching characteristics can be improved. This is because the electricfield strength during reverse bias is eased in a vicinity of a region inwhich the P-type diffused region 238 is formed, so that it is possibleto use a construction where in a region from the P-type diffused region238 to the N⁺-type drain region 218, the polysilicon gate electrode 222is provided opposite the N⁻-type epitaxial layer 210 with a thick fieldoxide film 236 in between.

[0172] Embodiment 2E

[0173]FIG. 2E is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 2E. A lateral short-channel DMOS 20E accordingto embodiment 2E has a similar construction to the lateral short-channelDMOS 20C according to embodiment 2C, with as shown in FIG. 2E, thedifference being that in a region from the P-type diffused region 238 tothe N⁺-type drain region 218, the polysilicon gate electrode 222 isprovided opposite the N⁻-type epitaxial layer 210 with the field oxidefilm 236 in between.

[0174] This means that in addition to the effects of the lateralshort-channel DMOS 20C according to embodiment 2C, the lateralshort-channel DMOS 20E according to embodiment 2E has the followingeffect. That is, the capacity between the gate and the source andbetween the gate and the drain can be reduced, so that the high-speedswitching characteristics can be further improved. This is because theelectric field strength during reverse bias is eased in a vicinity of aregion in which the P-type diffused region 238 is formed, so that it ispossible to use a construction where in a region from the P-typediffused region 238 to the N⁺-type drain region 218, the polysilicongate electrode 222 is provided opposite the N⁻-type epitaxial layer 210with a thick field oxide film 236 in between.

[0175] Embodiment 2F

[0176]FIG. 2F is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 2F. A lateral short-channel DMOS 20F accordingto embodiment 2F has a similar construction to the lateral short-channelDMOS 20E according to embodiment 2E, with as shown in FIG. 2F, thedifference being that a P⁻-type epitaxial layer 211, not the N⁻-typeepitaxial layer 210, is formed on the surface of the P⁻-typesemiconductor substrate 208.

[0177] In this way, according to the lateral short-channel DMOS 20Faccording to embodiment 2F, the P⁻-type epitaxial layer 211 is formed onthe surface of the P⁻-type semiconductor substrate 208, but in the sameway as the lateral short-channel DMOS 20E according to embodiment 2E,the N⁻-type well 212 is formed in the surface of the P⁻-type epitaxiallayer 211, the P-type well 214 including the channel forming region C isformed in a surface of the N⁻-type well 212, and the N⁺-type sourceregion 216 is formed in a surface of the P-type well 214. On the otherhand, in the same way as the lateral short-channel DMOS 20E according toembodiment 2E, the ON resistance lowering N-type well 234 is formed inthe surface of the P⁻-type epitaxial layer 211 so as to not contact theP-type well 214, and an N⁺-type drain region 218 is formed in a surfaceof the ON resistance lowering N-type well 234.

[0178] This means that the lateral short-channel DMOS 20F according toembodiment 2F has the same effect as the lateral short-channel DMOS 20Eaccording to embodiment 2E.

[0179] Embodiment 3A

[0180]FIG. 3A is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 3A of the present invention. A lateralshort-channel DMOS 30A according to this embodiment 3A is a lateralshort-channel DMOS according to a third aspect of the present invention,and as shown in FIG. 3A, has an N⁻-type well (first conductivity-typewell) 312 formed in a surface of a P⁻-type semiconductor substrate 310.A P-type well (second conductivity-type well) 314 including a channelforming region C is formed in a surface of the N⁻-type well 312, and anN⁺-type source region (first conductivity-type source region) 316 isformed in a surface of the P-type well 314. On the other hand, an ONresistance lowering N-type well (first conductivity-type ON resistancelowering well) 334 is formed in a surface of the P⁻-type semiconductorsubstrate 310 so as to contact the N⁻-type well 312 and to not contactthe P-type well 314. An N⁺-type drain region (first conductivity-typedrain region) 318 is formed in a surface of the ON resistance loweringN-type well 334.

[0181] A polysilicon gate electrode 322 is formed via a gate insulatingfilm 320 in at least an upper part of the channel forming region C, outof a region from the N⁺-type source region 316 to the N⁺-type drainregion 318, with the polysilicon gate electrode 322 being connected to agate resistance lowering metal layer 330.

[0182] This means that according to the lateral short-channel DMOS 30Aaccording to embodiment 3A, the ON resistance lowering N-type well 334is formed in the surface of the P⁻-type semiconductor substrate 310 soas to contact the N⁻-type well 312 and to not contact the P-type well314 and the N⁺-type drain region 318 is formed in the surface of the ONresistance lowering N-type well 334, so that when the DMOS 30A is ON,the ON resistance lowering N-type well 334 that has low resistanceprovides a large part of the current path from the N⁺-type drain region318 to the N⁺-type source region 316 and the overall ON resistance canbe sufficiently lowered even when the gate length is extended to lowerthe gate resistance. Accordingly, the lateral short-channel DMOS 30Aaccording to embodiment 3A has a low gate resistance and a low ONresistance, as well as superior high-speed switching characteristics andsuperior current driving characteristics.

[0183] According to the lateral short-channel DMOS 30A according toembodiment 3A, the ON resistance lowering N-type well 334 that includesa higher concentration of N-type dopant than the N⁻-type well 312 isprovided separately, so that the resistance when the DMOS 30A is ON canbe lowered without increasing the concentration of dopant in the N⁻-typewell 312 and there is no worsening in the breakdown characteristics ofthe lateral short-channel DMOS.

[0184] Also, according to the lateral short-channel DMOS 30A accordingto embodiment 3A, although the N⁻-type well 312 needs to be formedrelatively deeply from the surface of the P⁻-type semiconductorsubstrate 310 in order to maintain the breakdown characteristics of thelateral short-channel DMOS, the ON resistance lowering N-type well 334only needs to act as a current path from the N⁺-type drain region 318 tothe N⁺-type source region 316 and so may be formed relatively shallowlyfrom the surface of the P⁻-type semiconductor substrate 310. This meansthat little extension in the horizontal direction is required whenforming the ON resistance lowering N-type well 334, and as a result, theelement area of the lateral short-channel DMOS does not becomeparticularly large.

[0185] In the lateral short-channel DMOS 30A according to embodiment 3A,the depth of the N⁻-type well 312 is 5 μm, for example, the depth of theP-type well 314 is 1.5 μm, for example, the depth of the N⁺-type sourceregion 316 is 0.3 μm, for example, the depth of the N⁺-type drain region318 is 0.3 μm, for example, and the depth of the ON resistance loweringN-type well 334 is 2 μm, for example.

[0186] Also, in the lateral short-channel DMOS 30A according toembodiment 3A, the dopant concentration of the ON resistance loweringN-type well 334 is 1×10⁺¹⁹ ions/cm³, for example, and the dopantconcentration of the N⁻-type well 312 is 1×10⁺¹⁶ ions/cm³, for example.

[0187] Embodiment 3B

[0188]FIG. 3B is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 3B. A lateral short-channel DMOS 30B accordingto embodiment 3B has a similar structure to the lateral short-channelDMOS 30A according to embodiment 3A, with as shown in FIG. 3B, thedifference being that a P-type diffused region (second conductivity-typediffused region) 338 is formed in a region between the P-type well 314and the N⁺-type drain region 318 in a surface of the N⁻-type well 312 soas to not contact the P-type well 314.

[0189] According to the lateral short-channel DMOS 30B according toembodiment 3B, the following effect is obtained in addition to theeffects of the lateral short-channel DMOS 30A according to embodiment3A. That is, an electric field strength in a vicinity of the region inwhich the P-type diffused region 338 is formed is eased during reversebias, so that the breakdown characteristics can be stabilized further.

[0190] It should be noted that when the DMOS 30B is ON, the current fromthe N⁺-type drain region 318 to the N⁺-type source region 316 avoids theP-type diffused region 338 and flows in a deeper part (the N⁻-type well312) than the P-type diffused region 338, so that there is no increasein the ON resistance.

[0191] Embodiment 3C

[0192]FIG. 3C is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 3C. A lateral short-channel DMOS 30C accordingto embodiment 3C has a similar construction to the lateral short-channelDMOS 30B according to embodiment 3B, with as shown in FIG. 3C, thedifference being that the P-type diffused region 338 is formed so as tonot contact the ON resistance lowering N-type well 334.

[0193] This means that in addition to the effects of the lateralshort-channel DMOS 30B according to embodiment 3B, the lateralshort-channel DMOS 30C according to embodiment 3C has the followingeffect. That is, since the P-type diffused region 338 that is not biasedis constructed so as to not contact the ON resistance lowering N-typewell 334, it is possible to thoroughly suppress a worsening of thebreakdown characteristics and increases in leak currents.

[0194] Embodiment 3D

[0195]FIG. 3D is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 3D. A lateral short-channel DMOS 30D accordingto embodiment 3D has a similar construction to the lateral short-channelDMOS 30B according to embodiment 3B, with as shown in FIG. 3D, thedifference being that in a region from the P-type diffused region 338 tothe N⁺-type drain region 318, the polysilicon gate electrode 322 isprovided opposite the P⁻-type semiconductor substrate 310 with a fieldoxide film 336 in between.

[0196] This means that in addition to the effects of the lateralshort-channel DMOS 30B according to embodiment 3B, the lateralshort-channel DMOS 30D according to embodiment 3D has the followingeffect. That is, the capacity between the gate and the source andbetween the gate and the drain can be reduced, so that the high-speedswitching characteristics can be further improved. This is because theelectric field strength during reverse bias is eased in a vicinity of aregion in which the P-type diffused region 338 is formed, so that it ispossible to use a construction where in a region from the P-typediffused region 338 to the N⁺-type drain region 318, the polysilicongate electrode 322 is provided opposite the P⁻-type semiconductorsubstrate 310 with a thick field oxide film 336 in between.

[0197] Embodiment 3E

[0198]FIG. 3E is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 3E. A lateral short-channel DMOS 30E accordingto embodiment 3E has a similar construction to the lateral short-channelDMOS 30C according to the embodiment 3C, with as shown in FIG. 3E, thedifference being that in a region from the P-type diffused region 338 tothe N⁺-type drain region 318, the polysilicon gate electrode 322 isprovided opposite the P⁻-type semiconductor substrate 310 with the fieldoxide film 336 in between.

[0199] This means that in addition to the effects of the lateralshort-channel DMOS 30C according to embodiment 3C, the lateralshort-channel DMOS 30E according to embodiment 3E has the followingeffect. That is, the capacity between the gate and the source andbetween the gate and the drain can be reduced, so that the high-speedswitching characteristics can be further improved. This is because theelectric field strength during reverse bias is eased in a vicinity of aregion in which the P-type diffused region 338 is formed, so that it ispossible to use a construction where in a region from the P-typediffused region 338 to the N⁺-type drain region 318, the polysilicongate electrode 322 is provided opposite the P⁻-type semiconductorsubstrate 310 with a thick field oxide film 336 in between.

[0200] Lateral short-channel DMOS according to the present inventionhave been described above with embodiments 1A to 3E as examples, andnext the surface layout of the lateral short-channel DMOS according tothe present invention will be described with reference to FIGS. 4A and4B. FIGS. 4A and 4B are plan views of the lateral short-channel DMOS 30Daccording to embodiment 3D. FIG. 4A is a plan view showing thepolysilicon gate electrode 322 and a surface of the P⁻-typesemiconductor substrate. FIG. 4B is a plan view in which a sourceelectrode 326, a drain electrode 328, and the gate resistance loweringmetal layer 330 have been added to the structure shown in FIG. 4A. Asshown in FIGS. 4A and 4B, the lateral short-channel DMOS 30D isconstructed with the N⁺-type source region 316 disposed in the centerbeing surrounded by the N⁺-type drain region 318 that is disposed in anouter periphery. The polysilicon gate electrode 322 is disposed betweenthe N⁺-type source region 316 and the N⁺-type drain region 318. Itshould be noted that the symbol “S” in FIG. 4A represents a P-type well.Also, the ON resistance lowering N-type well 334 and the P-type diffusedregion 338 have been omitted from FIGS. 4A and 4B.

[0201]FIG. 5 is a cross-sectional view of the lateral short-channel DMOS30D according to embodiment 3D. In this drawing, a wider region is shownthan in FIG. 3D. As shown in FIG. 5, the lateral short-channel DMOS 30Dis constructed so as to be surrounded by the N⁺-type drain region 318disposed in an outer periphery thereof with the polysilicon gateelectrode 322 disposed inside the N⁺-type drain region 318 and theN⁺-type source region 316 disposed inside the polysilicon gate electrode322. This means that as shown in FIGS. 4 and 5, the lateralshort-channel DMOS 30D is a lateral short-channel DMOS with a large gatewidth and superior current driving characteristics.

[0202] Next, an example of where the lateral short-channel DMOSaccording to the present invention is integrated with other elementswill be described with reference to FIG. 6. FIG. 6 is a cross-sectionalview of a semiconductor device in which the lateral short-channel DMOS20E is integrated with other elements. As shown in FIG. 6, thissemiconductor device 28 includes the N-channel lateral short-channelDMOS 20E, a P-channel MOS transistor 21, an N-channel MOS transistor 23,a P-channel MOS transistor 22, an NPN bipolar transistor 25, and a PNPbipolar transistor 24. These respective other elements are formed insidean N⁻-type epitaxial layer 210 formed on the surface of a P⁻-typesemiconductor substrate.

[0203] In the lateral short-channel DMOS 20E, the N⁻-type well 212 isformed inside the N⁻-type epitaxial layer 210, and the P-type well andthe N⁺-type source region is formed in this N⁻-type well. This meansthat according to the semiconductor device 28, it is possible to controlthe breakdown characteristics of the lateral short-channel DMOS 20E viathe dopant concentration of the N⁻-type well 212. As a result, thedopant concentration of the N⁻-type epitaxial layer 210 can be set at anappropriate concentration (for example, a lower concentration than theN⁻-type well 212) for the other elements (for example, the N-channel MOStransistor 23 and the P-channel MOS transistor 22), so that asemiconductor device with superior characteristics can be provided.

[0204] Embodiment 4

[0205]FIGS. 7a to 7 f are diagrams showing manufacturing processesduring a method of manufacturing a lateral short-channel DMOS accordingto embodiment 4. The method of manufacturing a lateral short-channelDMOS according to embodiment 4 is a method of manufacturing the lateralshort-channel DMOS 10D according to embodiment 1D. This method ofmanufacturing a lateral short-channel DMOS according to embodiment 4will be described with reference to FIGS. 7a to 7 f.

[0206] As shown in FIGS. 7a to 7 f, the method of manufacturing alateral short-channel DMOS according to embodiment 4 includes the firstprocess (a) to the sixth process (f) described below.

[0207] (a) First Process

[0208] A semiconductor substrate where the N⁻-type epitaxial layer 110is formed on a surface of a semiconductor substrate 108 composed of aP⁻-type silicon substrate is prepared. The dopant concentration of theepitaxial layer 110 is set at 1×10⁺¹⁶ ions/cm³, for example.

[0209] (b) Second Process

[0210] Next, a first ion implanting mask 152 with a predeterminedopening is formed on a surface of the N⁻-type epitaxial layer 110 andphosphorous ions, for example, are implanted as an N-type dopant withthe first ion implanting mask 152 as a mask to form the ON resistancelowering N-type well 134. Here, the dopant concentration is 1×10⁺¹⁹ions/cm³, for example.

[0211] (c) Third Process

[0212] Next, after the first ion implanting mask 152 has been removed, asecond ion implanting mask 154 with a predetermined opening is formed onthe surface of the N⁻-type epitaxial layer 110 and boron ions, forexample, are implanted as a P-type dopant with the second ion implantingmask 154 as a mask to form the P-type well 114 that does not contact theON resistance lowering N-type well 134 and also form the P-type diffusedregion 138 in a region of the ON resistance lowering N-type well 134that is opposite the P-type well 114. Here, the dopant concentration is3×10⁺¹⁷ ions/cm³, for example. It should be noted that it is alsopossible to form the P-type well 114 and the P-type diffused region 138in separate steps.

[0213] (d) Fourth Process

[0214] Next, after the second ion implanting mask 154 has been removed,the field oxide film 136 that includes a predetermined opening is formedon the surface of the N⁻-type epitaxial layer 110, and the gateinsulating film 120 is formed by thermal oxidization at the opening ofthe field oxide film 136.

[0215] (e) Fifth Process

[0216] Next, the polysilicon gate electrode 122 is formed in apredetermined region on upper surfaces of the gate insulating film 120and the field oxide film 136.

[0217] (f) Sixth Process

[0218] Next, after a resist 156 has been formed, the resist 156, thepolysilicon gate electrode 122, and the field oxide film 136 are used asa mask and arsenic ions, for example, are implanted as an N-type dopantto form the N⁺-type source region 116 and the N⁺-type drain region 118.

[0219] After this, the implanted dopant is activated, and then aninterlayer dielectric 124 is formed. Next, after a predetermined contacthole has been opened in the interlayer dielectric 124, a metal layer isformed. After this, the metal layer is patterned to form a sourceelectrode 126, a drain electrode 128, and the gate resistance loweringmetal layer 130. Next, the semiconductor substrate 108 is connected toground 132, thereby completing the lateral short-channel DMOS 10D.

[0220] As shown above, according to the method of manufacturing alateral short-channel DMOS according to embodiment 4, it is possible tomanufacture the superior lateral short-channel DMOS 10D according toembodiment 1D using a relatively simple method.

[0221] It should be noted that when manufacturing the lateralshort-channel DMOS 10B according to embodiment 1B, in the fourth process(d) of the above method of manufacturing, the field oxide film 136 maybe opened in a region from the P-type diffused region 138 to the N⁺-typedrain region 118 (the region that will become the N⁺-type drain region118).

[0222] Also, when manufacturing the lateral short-channel DMOS 10Aaccording to embodiment 1A, in the third process (c) of the above methodof manufacturing, a mask with a part that is not open corresponding tothe P-type diffused region 138 may be used as the second ion implantingmask 154.

[0223] Also, when manufacturing the lateral short-channel DMOS 10Eaccording to embodiment 1E, in the second and third processes (b) and(c) of the above method of manufacturing, the P-type diffused region 138may be formed so as to not contact the ON resistance lowering N-typewell 134.

[0224] Also, when manufacturing the lateral short-channel DMOS 10Caccording to embodiment 1C, in the second and third processes (b) and(c) of the above method of manufacturing, the P-type diffused region 138may be formed so as to not contact the ON resistance lowering N-typewell 134, and in the fourth process (d) the field oxide film 136 may beopened in a region from the P-type diffused region 138 to the N⁺-typedrain region 118.

[0225] Embodiment 5

[0226]FIGS. 8a to 8 g are diagrams showing manufacturing processesduring a method of manufacturing a lateral short-channel DMOS accordingto embodiment 5. The method of manufacturing a lateral short-channelDMOS according to embodiment 5 is a method of manufacturing the lateralshort-channel DMOS 20D according to embodiment 2D. This method ofmanufacturing a lateral short-channel DMOS according to embodiment 5will now be described with reference to FIGS. 8a to 8 g.

[0227] As shown in FIGS. 8a to 8 g, the method of manufacturing alateral short-channel DMOS according to embodiment 5 includes the firstprocess (a) to the seventh process (g) described below.

[0228] (a) First Process

[0229] A semiconductor substrate where the N⁻-type epitaxial layer 210is formed on a surface of a semiconductor substrate 208 composed of aP⁻-type silicon substrate is prepared. The dopant concentration of theN⁻-type epitaxial layer 210 is set at 5×10⁺¹⁵ ions/cm³, for example.

[0230] (b) Second Process

[0231] Next, a first ion implanting mask 250 with a predeterminedopening is formed on a surface of the N⁻-type epitaxial layer 210 andphosphorous ions, for example, are implanted as an N-type dopant withthe first ion implanting mask 250 as a mask to form the N⁻-type well212. Here, the dopant concentration is 1×10⁺¹⁶ ions/cm³, for example.

[0232] (c) Third Process

[0233] Next, after the first ion implanting mask 250 has been removed, asecond ion implanting mask 252 with a predetermined opening is formed onthe surface of the N⁻-type epitaxial layer 210 and phosphorus ions, forexample, are implanted at a higher concentration than in the secondprocess as an N-type dopant with the second ion implanting mask 252 as amask to form the ON resistance lowering N-type well 234 that contact theN⁻-type well 212. Here, the dopant concentration is 1×10⁺¹⁹ ions/cm³,for example.

[0234] (d) Fourth Process

[0235] Next, after the second ion implanting mask 252 has been removed,a third ion implanting mask 254 with a predetermined opening is formedon the surface of the N⁻-type epitaxial layer 210 and boron ions, forexample, are implanted as a P-type dopant with the third ion implantingmask 254 as a mask to form the P-type well 214 that does not contact theON resistance lowering N-type well 234 and also form the P-type diffusedregion 238 in a region of the ON resistance lowering N-type well 234that is opposite the P-type well 214. Here, the dopant concentration is3×10⁺¹⁷ ions/cm³, for example. It should be noted that it is alsopossible to form the P-type well 214 and the P-type diffused region 238in separate steps.

[0236] (e) Fifth Process

[0237] Next, after the third ion implanting mask 254 has been removed,the field oxide film 236 with a predetermined opening is formed on thesurface of the N⁻-type epitaxial layer 210, and the gate insulating film220 is formed by thermal oxidization at the opening of the field oxidefilm 236.

[0238] (f) Sixth Process

[0239] Next, the polysilicon gate electrode 222 is formed in apredetermined region on upper surfaces of the gate insulating film 220and the field oxide film 236.

[0240] (g) Seventh Process

[0241] Next, after a resist 256 has been formed, the resist 256, thepolysilicon gate electrode 222, and the field oxide film 236 are used asa mask and arsenic ions, for example, are implanted as an N-type dopantto form the N⁺-type source region 216 and the N⁺-type drain region 218.

[0242] After this, the implanted dopant is activated, and then aninterlayer dielectric 224 is formed. Next, after a predetermined contacthole has been opened in the interlayer dielectric 224, a metal layer isformed. After this, the metal layer is patterned to form a sourceelectrode 226, a drain electrode 228, and the gate resistance loweringmetal layer 230. Next, the semiconductor substrate 208 is connected toground 232, thereby completing the lateral short-channel DMOS 20D.

[0243] As shown above, according to the method of manufacturing alateral short-channel DMOS according to embodiment 5, it is possible tomanufacture the superior lateral short-channel DMOS 20D according toembodiment 2D using a relatively simple method.

[0244] It should be noted that when manufacturing the lateralshort-channel DMOS 20B according to embodiment 2B, in the fifth process(e) of the above method of manufacturing, the field oxide film 236 maybe opened in a region from the P-type diffused region 238 to the N⁺-typedrain region 218 (the region that will become the N⁺-type drain region218).

[0245] Also, when manufacturing the lateral short-channel DMOS 20Aaccording to embodiment 2A, in the fourth process (d) of the abovemethod of manufacturing, a mask with a part that is not opencorresponding to the P-type diffused region 238 may be used as the thirdion implanting mask 254.

[0246] Also, when manufacturing the lateral short-channel DMOS 20Eaccording to embodiment 2E, in the third and fourth processes (c) and(d) of the above method of manufacturing, the P-type diffused region 238may be formed so as to not contact the ON resistance lowering N-typewell 234.

[0247] Also, when manufacturing the lateral short-channel DMOS 20Caccording to embodiment 2C, in the third and fourth processes (c) and(d) of the above method of manufacturing, the P-type diffused region 238may be formed so as to not contact the ON resistance lowering N-typewell 234, and in the fifth process (e) the field oxide film 236 may beopened in a region from the P-type diffused region 238 to the N⁺-typedrain region 218.

[0248] Also, when manufacturing the lateral short-channel DMOS 20Faccording to embodiment 2F, in the first process of the above method ofmanufacturing, a semiconductor substrate where the P⁻-type epitaxiallayer 211 is formed on a surface of a semiconductor substrate 208composed of a P⁻-type silicon substrate may be prepared. A substratewith a dopant concentration of 5×10⁺¹⁵ ions/cm³, for example, is used asthe P⁻-type epitaxial layer 211.

[0249] Embodiment 6

[0250]FIGS. 9a to 9 g are diagrams showing manufacturing processesduring a method of manufacturing a lateral short-channel DMOS accordingto embodiment 6. The method of manufacturing a lateral short-channelDMOS according to embodiment 6 is a method of manufacturing the lateralshort-channel DMOS 30D according to embodiment 3D. This method ofmanufacturing a lateral short-channel DMOS according to embodiment 6will now be described with reference to FIGS. 9a to 9 g.

[0251] As shown in FIGS. 9a to 9 g, the method of manufacturing alateral short-channel DMOS according to embodiment 6 includes the firstprocess (a) to the seventh process (g) described below.

[0252] (a) First Process

[0253] A semiconductor substrate 310 composed of a P⁻-type siliconsubstrate is prepared.

[0254] (b) Second Process

[0255] Next, a first ion implanting mask 350 with a predeterminedopening is formed on a surface of this semiconductor substrate 310 andphosphorous ions, for example, are implanted as an N-type dopant withthe first ion implanting mask 350 as a mask to form the N⁻-type well312. Here, the dopant concentration is 1×10⁺¹⁶ ions/cm³, for example.

[0256] (c)Third Process

[0257] Next, after the first ion implanting mask 350 has been removed, asecond ion implanting mask 352 with a predetermined opening is formed onone surface of the semiconductor substrate 310 and phosphorus ions, forexample, are implanted at a higher concentration than in the secondprocess as an N-type dopant with the second ion implanting mask 352 as amask to form the ON resistance lowering N-type well 334 that contact theN⁻-type well 312. Here, the dopant concentration is 1×10⁺¹⁹ ions/cm³,for example.

[0258] (d) Fourth Process

[0259] Next, after the second ion implanting mask 352 has been removed,a third ion implanting mask 354 with a predetermined opening is formedon one surface of the semiconductor substrate 310 and boron ions, forexample, are implanted as a P-type dopant with the third ion implantingmask 354 as a mask to form the P-type well 314 that does not contact theON resistance lowering N-type well 334 and also form the P-type diffusedregion 338 in a region of the ON resistance lowering N-type well 334that is opposite the P-type well 314. Here, the dopant concentration is3×10⁺¹⁷ ions/cm³, for example. It should be noted that it is alsopossible to form the P-type well 314 and the P-type diffused region 338in separate steps.

[0260] (e) Fifth Process

[0261] Next, after the third ion implanting mask 354 has been removed,the field oxide film 336 with a predetermined opening is formed on onesurface of the semiconductor substrate 310, and the gate insulating film320 is formed by thermal oxidization at the opening of the field oxidefilm 336.

[0262] (f) Sixth Process

[0263] Next, the polysilicon gate electrode 322 is formed in apredetermined region on upper surfaces of the gate insulating film 320and the field oxide film 336.

[0264] (g) Seventh Process

[0265] Next, after a resist 356 has been formed, the resist 356, thepolysilicon gate electrode 322, and the field oxide film 336 are used asa mask and arsenic ions, for example, are implanted as an N-type dopantto form the N⁺-type source region 316 and the N⁺-type drain region 318.

[0266] After this, the implanted dopant is activated, and then aninterlayer dielectric 324 is formed. Next, after a predetermined contacthole has been opened in the interlayer dielectric 324, a metal layer isformed. After this, the metal layer is patterned to form a sourceelectrode 326, a drain electrode 328, and the gate resistance loweringmetal layer 330. Next, the semiconductor substrate 310 is connected toground 332, thereby completing the lateral short-channel DMOS 30D.

[0267] As shown above, according to the method of manufacturing alateral short-channel DMOS according to embodiment 6, it is possible tomanufacture the superior lateral short-channel DMOS 30D according toembodiment 3D using a relatively simple method.

[0268] It should be noted that when manufacturing the lateralshort-channel DMOS 30B according to embodiment 3B, in the fifth process(e) of the above method of manufacturing, the field oxide film 336 maybe opened in a region from the P-type diffused region 338 to the N⁺-typedrain region 318 (the region that will become the N⁺-type drain region318).

[0269] Also, when manufacturing the lateral short-channel DMOS 30Aaccording to embodiment 3A, in the fourth process (d) of the abovemethod of manufacturing, a mask with a part that is not opencorresponding to the P-type diffused region 338 may be used as the thirdion implanting mask 354.

[0270] Also, when manufacturing the lateral short-channel DMOS 30Eaccording to embodiment 3E, in the third and fourth processes (c) and(d) of the above method of manufacturing, the P-type diffused region 338may be formed so as to not contact the ON resistance lowering N-typewell 334.

[0271] Also, when manufacturing the lateral short-channel DMOS 30Caccording to embodiment 3C, in the third and fourth processes (c) and(d) of the above method of manufacturing, the P-type diffused region 338may be formed so as to not contact the ON resistance lowering N-typewell 334, and in the fifth process (e) the field oxide film 336 may beopened in a region from the P-type diffused region 338 to the N⁺-typedrain region 318.

[0272] Embodiment 7E

[0273]FIG. 10 is a cross-sectional view of a lateral short-channel DMOS40E according to embodiment 7E. The lateral short-channel DMOS 40E isthe lateral short-channel DMOS 10E according to embodiment 1E with theconductivity types (except that of the semiconductor substrate) havingbeen reversed. With the lateral short-channel DMOS 40E the same effectsas the lateral short-channel DMOS 10E can be obtained.

[0274] That is, when the DMOS 40E is ON, the ON resistance loweringP-type well 434 that has low resistance provides a large part of thecurrent path from the P⁺-type source region 416 to the P⁺-type drainregion 418, so that the overall ON resistance can be sufficientlylowered even when the gate length is extended to lower the gateresistance. Accordingly, the lateral short-channel DMOS has a low gateresistance and a low ON resistance, as well as superior high-speedswitching characteristics and superior current driving characteristics.

[0275] Also, the ON resistance lowering P-type well 434 that includes ahigher concentration of P-type dopant than the P⁻-type epitaxial layer410 is provided separately, so that the resistance when the DMOS 40E isON can be lowered without increasing the concentration of dopant in theP⁻-type epitaxial layer 410 itself and there is no worsening in thebreakdown characteristics of the lateral short-channel DMOS.

[0276] Also, since the N-type diffused region 438 is formed in theP⁻-type epitaxial layer 410, the electric field strength in a vicinityof a region in which the N-type diffused region 438 is formed is easedduring reverse bias, so that the breakdown characteristics can bestabilized further. It should be noted that when the DMOS 40E is ON thecurrent from the P⁺-type source region 416 to the P⁺-type drain region418 avoids the N-type diffused region 438 and flows in a deeper part(the P⁻-type epitaxial layer 410) than the N-type diffused region 438,so that there is no increase in the ON resistance due to the provisionof the N-type diffused region 438.

[0277] Also, since the N-type diffused region 438 that is not biased isconstructed so as to not contact the ON resistance lowering P-type well434, it is possible to thoroughly suppress a worsening of the breakdowncharacteristics and increases in leak currents.

[0278] Also, since the polysilicon gate electrode 422 is providedopposite the P⁻-type epitaxial layer 410 with the field oxide film 436in between in a region from the N-type diffused region 438 to theP⁺-type drain region 418, the capacity between the gate and the sourceand between the gate and the drain can be reduced, which furtherimproves the high-speed switching characteristics.

[0279] Embodiment 8E

[0280]FIG. 11A is a cross-sectional view of a lateral short-channel DMOS50E according to embodiment 8E. The lateral short-channel DMOS 50E isthe lateral short-channel DMOS 20E according to embodiment 2E with theconductivity types (except that of the semiconductor substrate) havingbeen reversed. With the lateral short-channel DMOS 50E the same effectsas the lateral short-channel DMOS 20E can be obtained.

[0281] That is, when the DMOS 50E is ON, the ON resistance loweringP-type well 534 that has low resistance provides a large part of thecurrent path from the P⁺-type source region 516 to the P⁺-type drainregion 518, so that the overall ON resistance can be sufficientlylowered even when the gate length is extended to lowered the gateresistance. Accordingly, the lateral short-channel DMOS has a low gateresistance and a low ON resistance, as well as superior high-speedswitching characteristics and superior current driving characteristics.

[0282] Also, the ON resistance lowering P-type well 534 that includes ahigher concentration of P-type dopant than the P⁻-type well 512 isprovided separately, so that the resistance when the DMOS 50E is ON canbe lowered without increasing the concentration of dopant in the P⁻-typewell 512 itself and there is no worsening in the breakdowncharacteristics of the lateral short-channel DMOS.

[0283] Also, by forming the P⁻-type well 512 inside the P⁻-typeepitaxial layer 510, even in a semiconductor device, or the like, inwhich the lateral short-channel DMOS is integrated with other elements(logic elements, for example), the breakdown characteristics of thelateral short-channel DMOS can be controlled via the dopantconcentration of the P⁻-type well 512. As a result, it is possible toset the dopant concentration of the P⁻-type epitaxial layer 510 at asuitable concentration (for example, a lower concentration than theP⁻-type well 512) for the other elements (for example, logic elements)and thereby provide a semiconductor device with superiorcharacteristics.

[0284] Since the N-type diffused region 538 is formed in the P⁻-typewell 512, the electric field strength in a vicinity of a region in whichthe N-type diffused region 538 is formed is eased during reverse bias,so that the breakdown characteristics can be stabilized further. Itshould be noted that when the DMOS 50E is ON, the current from theP⁺-type source region 516 to the P⁺-type drain region 518 avoids theN-type diffused region 538 and flows in a deeper part (the P⁻-type well512) than the N-type diffused region 538, so that there is no increasein the ON resistance due to the provision of the N-type diffused region538.

[0285] Also, since the N-type diffused region 538 that is not biased isconstructed so as to not contact the ON resistance lowering P-type well534, it is possible to thoroughly suppress a worsening of the breakdowncharacteristics and increases in leak currents.

[0286] Also, since the polysilicon gate electrode 522 is providedopposite the P⁻-type epitaxial layer 510 with the field oxide film 536in between in a region from the N-type diffused region 538 to theP⁺-type drain region 518, the capacity between the gate and the sourceand between the gate and the drain can be reduced, which furtherimproves the high-speed switching characteristics.

[0287] Embodiment 8F

[0288]FIG. 11B is a cross-sectional view of a lateral short-channel DMOSaccording to embodiment 8F. A lateral short-channel DMOS 5OF has asimilar construction to the lateral short-channel DMOS 50E according toembodiment 8E, with as shown in FIG. 11B, the difference being that inan N⁻-type epitaxial layer 511, not the P⁻-type epitaxial layer 510, isformed on the surface of the P⁻-type semiconductor substrate 508.

[0289] In this way, according to the lateral short-channel DMOS 5OFaccording to embodiment 8F, the N⁻-type epitaxial layer 511 is formed onthe surface of the P⁻-type semiconductor substrate 508, but in the sameway as the lateral short-channel DMOS 50E according to embodiment 8E,the P⁻-type well 512 is formed in the surface of the N⁻-type epitaxiallayer 511, the N-type well 514 including the channel forming region C isformed in a surface of the P⁻-type well 512, and the P⁺-type sourceregion 516 is formed in a surface of the N-type well 514. On the otherhand, in the same way as the lateral short-channel DMOS 50E according toembodiment 8E, the ON resistance lowering N-type well 534 is formed inthe surface of the N⁻-type epitaxial layer 511 so as to not contact theN-type well 514, and a P⁺-type drain region 518 is formed in a surfaceof the ON resistance lowering P-type well 534.

[0290] This means that the lateral short-channel DMOS 50F according toembodiment 8F has the same effects as the lateral short-channel DMOS 50Eaccording to embodiment 8E.

[0291] Embodiment 9E

[0292]FIG. 12 is a cross-sectional view of a lateral short-channel DMOS60E according to embodiment 9E. The lateral short-channel DMOS 60E isthe lateral short-channel DMOS 30E according to embodiment 3E with theconductivity types (except that of the semiconductor substrate) havingbeen reversed. With the lateral short-channel DMOS 60E the same effectsas the lateral short-channel DMOS 30E can be obtained.

[0293] That is, when the DMOS 60E is ON, the ON resistance loweringP-type well 634 that has low resistance provides a large part of thecurrent path from the P⁺-type source region 616 to the P⁺-type drainregion 618, so that the overall ON resistance can be sufficientlylowered even when the gate length is extended to lower the gateresistance. Accordingly, the lateral short-channel DMOS has a low gateresistance and a low ON resistance, as well as superior high-speedswitching characteristics and superior current driving characteristics.

[0294] Also, the ON resistance lowering P-type well 634 that includes ahigher concentration of P-type dopant than the P⁻-type well 612 isprovided separately, so that the resistance when the DMOS 60E is ON canbe lowered without increasing the concentration of dopant in the P⁻-typewell 612 itself and there is no worsening in the breakdowncharacteristics of the lateral short-channel DMOS.

[0295] It should be noted that in this lateral short-channel DMOS,although the P⁻-type well 612 needs to be formed relatively deeply fromthe surface of the P⁻-type semiconductor substrate 610 to maintain thebreakdown characteristics of the lateral short-channel DMOS, the ONresistance lowering P-type well 634 only needs to act as a current pathfrom the P⁺-type source region 616 to the P⁺-type drain region 618 andtherefore may be formed relatively shallowly from the surface of thePN⁻-type semiconductor substrate 610. This means that little extensionin the horizontal direction is required when forming the ON resistancelowering N-type well 634, and as a result the element area of thelateral short-channel DMOS does not become particularly large.

[0296] Also, since the N-type diffused region 638 is formed inside theP⁻-type well 612, the electric field strength in the vicinity of theregion in which the N-type diffused region 638 is eased during reversebias and it is possible to further stabilize the breakdowncharacteristics. It should be noted that when the DMOS 60E is ON, thecurrent from the P⁺-type source region 616 to the P⁺-type drain region618 avoids the N-type diffused region 638 and flows in a deeper part(the P⁻-type well 612) than the N-type diffused region 638, so thatthere is no increase in the ON resistance.

[0297] Since the N-type diffused region 638 that is not biased isconstructed so as to not contact the ON resistance lowering P-type well634, it is possible to thoroughly suppress a worsening of the breakdowncharacteristics and increases in leak currents.

[0298] Also, since the polysilicon gate electrode 622 is providedopposite the P⁻-type semiconductor substrate 610 with the field oxidefilm 636 in between in a region from the N-type diffused region 638 tothe P⁺-type drain region 618, the capacity between the gate and thesource and between the gate and the drain can be reduced, which furtherimproves the high-speed switching characteristics.

[0299] As described above, according to the present invention, it ispossible to provide a lateral short-channel DMOS with low gateresistance and low ON resistance, as well as superior high-speedswitching characteristics and superior current driving characteristics.Also, according to the present invention, it is possible to manufacturethe above superior lateral short-channel DMOS using a relatively simplemethod.

1. A lateral short-channel DMOS comprising: a first conductivity-typeepitaxial layer formed on a surface of a semiconductor substrate; asecond conductivity-type well that is formed in a surface of the firstconductivity-type epitaxial layer and includes a channel forming region,the second conductivity type being an inverse of the first conductivitytype; a first conductivity-type source region that is formed in thesecond conductivity-type well; a first conductivity-type ON resistancelowering well that is formed in the surface of the firstconductivity-type epitaxial layer so as to not contact the secondconductivity-type well and includes a higher concentration of a firstconductivity-type dopant than the first conductivity-type epitaxiallayer; a first conductivity-type drain region formed in a surface of thefirst conductivity-type ON resistance lowering well; a gate electrodeformed, via a gate insulating film, in at least an upper part of thechannel forming region out of a region from the first conductivity-typesource region to the first conductivity-type drain region; and a gateresistance lowering metal layer connected to the gate electrode.
 2. Alateral short-channel DMOS according to claim 1, wherein a secondconductivity-type diffused region is formed in a floating state in thesurface of the first conductivity-type epitaxial layer in a regionbetween the second conductivity-type well and the firstconductivity-type drain region so as to not contact the secondconductivity-type well.
 3. A lateral short-channel DMOS according toclaim 2, wherein the second conductivity-type diffused region is formedso as to not contact the first conductivity-type ON resistance loweringwell.
 4. A lateral short-channel DMOS according to claim 2, wherein in aregion from the second conductivity-type diffused region to the firstconductivity-type drain region, the gate electrode is provided oppositethe first conductivity-type epitaxial layer with a field oxide film inbetween.
 5. A lateral short-channel DMOS comprising: an epitaxial layerformed on a surface of a semiconductor substrate; a firstconductivity-type well formed in a surface of the epitaxial layer; asecond conductivity-type well that is formed in a surface of the firstconductivity-type well and includes a channel forming region, the secondconductivity type being an inverse of the first conductivity type; afirst conductivity-type source region that is formed in a surface of thesecond conductivity-type well; a first conductivity-type ON resistancelowering well that is formed in a surface of the epitaxial layer so asto contact the first conductivity-type well and to not contact thesecond conductivity-type well, and includes a higher concentration of afirst conductivity-type dopant than the first conductivity-type well; afirst conductivity-type drain region formed in a surface of the firstconductivity-type ON resistance lowering well; a gate electrode formed,via a gate insulating film, in an upper part of at least the channelforming region out of a region from the first conductivity-type sourceregion to the first conductivity-type drain region; and a gateresistance lowering metal layer connected to the gate electrode.
 6. Alateral short-channel DMOS according to claim 5, wherein a secondconductivity-type diffused region is formed in a floating state in asurface of the first conductivity-type well in a region between thesecond conductivity-type well and the first conductivity-type drainregion so as to not contact the second conductivity-type well.
 7. Alateral short-channel DMOS according to claim 6, wherein the secondconductivity-type diffused region is formed so as to not contact thefirst conductivity-type ON resistance lowering well.
 8. A lateralshort-channel DMOS according to claim 6, wherein in a region from thesecond conductivity-type diffused region to the first conductivity-typedrain region, the gate electrode is provided opposite the epitaxiallayer with a field oxide film in between.
 9. A lateral short-channelDMOS, comprising: a first conductivity-type well formed in a surface ofa semiconductor substrate; a second conductivity-type well that isformed in a surface of the first conductivity-type well and includes achannel forming region, the second conductivity type being an inverse ofthe first conductivity type; a first conductivity-type source regionthat is formed in a surface of the second conductivity-type well; afirst conductivity-type ON resistance lowering well that is formed in asurface of the semiconductor substrate so as to contact the firstconductivity-type well and not contact the second conductivity-typewell, and includes a higher concentration of a first conductivity-typedopant than the first conductivity-type well; a first conductivity-typedrain region formed in a surface of the first conductivity-type ONresistance lowering well; a gate electrode formed, via a gate insulatingfilm, in an upper part of at least the channel forming region out of aregion from the first conductivity-type source region to the firstconductivity-type drain region; and a gate resistance lowering metallayer connected to the gate electrode.
 10. A lateral short-channel DMOSaccording to claim 9, wherein a second conductivity-type diffused regionis formed in a floating state in a surface of the firstconductivity-type well in a region between the second conductivity-typewell and the first conductivity-type drain region so as to not contactthe second conductivity-type well.
 11. A lateral short-channel DMOSaccording to claim 10, wherein the second conductivity-type diffusedregion is formed so as to not contact the first conductivity-type ONresistance lowering well.
 12. A lateral short-channel DMOS according toclaim 10 wherein in a region from the second conductivity-type diffusedregion to the first conductivity-type drain region, the gate electrodeis provided opposite the semiconductor substrate with a field oxide filmin between.
 13. A method of manufacturing a lateral short-channel DMOSaccording to claim 1, comprising the following steps in order: (a) afirst step of preparing the semiconductor substrate with the firstconductivity-type epitaxial layer formed on the surface thereof; (b) asecond step of forming a first ion implanting mask with a predeterminedopening on a surface of the first conductivity-type epitaxial layer andforming the first conductivity-type ON resistance lowering well byimplanting first conductivity-type dopant with the first ion implantingmask as a mask; (c) a third step of forming, after removal of the firstion implanting mask, a second ion implanting mask with a predeterminedopening on the surface of the first conductivity-type epitaxial layerand forming the second conductivity-type well so as to not contact thefirst conductivity-type ON resistance lowering well by implanting secondconductivity-type dopant with the second ion implanting mask as a mask;(d) a fourth step of forming, after removal of the second ion implantingmask, a field oxide film with a predetermined opening in the surface ofthe first conductivity-type epitaxial layer and forming the gateinsulating film by thermal oxidization at the opening in the field oxidefilm; (e) a fifth step of forming the gate electrode in a predeterminedregion on the gate insulating film; and (f) a sixth step of forming thefirst conductivity-type source region and the first conductivity-typedrain region by implanting first conductivity-type dopant with at leastthe gate electrode and the field oxide film as a mask.
 14. A method ofmanufacturing a lateral short-channel DMOS according to claim 13,wherein in the third step, a second conductivity-type diffused region isformed in a floating state in a region between the secondconductivity-type well and the first conductivity-type drain region soas to not contact the second conductivity-type well.
 15. A method ofmanufacturing a lateral short-channel DMOS according to claim 14,wherein in the third step, the second conductivity-type diffused regionis formed so as to not contact the first conductivity-type ON resistancelowering well.
 16. A method of manufacturing a lateral short-channelDMOS according to claim 14, wherein in the fourth step, the field oxidefilm is formed so as to include a region from the secondconductivity-type diffused region to the first conductivity-type drainregion.
 17. A method of manufacturing a lateral short-channel DMOSaccording to claim 5, comprising the following steps in order: (a) afirst step of preparing the semiconductor substrate with the epitaxiallayer formed on the surface thereof; (b) a second step of forming afirst ion implanting mask with a predetermined opening on a surface ofthe epitaxial layer and forming the first conductivity-type well byimplanting first conductivity-type dopant into the semiconductorsubstrate with the first ion implanting mask as a mask; (c) a third stepof forming, after removal of the first ion implanting mask, a second ionimplanting mask with a predetermined opening on the surface of theepitaxial layer and forming the first conductivity-type ON resistancelowering well so as to contact the first conductivity-type well byimplanting first conductivity-type dopant with a higher concentrationthan the second step with the second ion implanting mask as a mask; (d)a fourth step of forming, after removal of the second ion implantingmask, a third ion implanting mask with a predetermined opening on thesurface of the epitaxial layer and forming the second conductivity-typewell so as to not contact the first conductivity-type ON resistance wellby implanting second conductivity-type dopant with the third ionimplanting mask as a mask; (e) a fifth step of forming, after removal ofthe third ion implanting mask, a field oxide film with a predeterminedopening in the surface of the epitaxial layer and forming the gateinsulating film by thermal oxidization at the opening in the field oxidefilm; (f) a sixth step of forming the gate electrode in a predeterminedregion on the gate insulating film; and (g) a seventh step of formingthe first conductivity-type source region and the firstconductivity-type drain region by implanting first conductivity-typedopant with at least the gate electrode and the field oxide film as amask.
 18. A method of manufacturing a lateral short-channel DMOSaccording to claim 17, wherein in the fourth step, a secondconductivity-type diffused region is formed in a floating state in aregion of the first conductivity-type well between the secondconductivity-type well and the first conductivity-type drain region soas to not contact the second conductivity-type well.
 19. A method ofmanufacturing a lateral short-channel DMOS according to claim 18,wherein in the fourth step, the second conductivity-type diffused regionis formed so as to not contact the first conductivity-type ON resistancelowering well.
 20. A method of manufacturing a lateral short-channelDMOS according to claim 18, wherein in the fifth step, the field oxidefilm is formed so as to include a region from the secondconductivity-type diffused region to the first conductivity-type drainregion.
 21. A method of manufacturing a lateral short-channel DMOSaccording to claim 9, comprising the following steps in order: (a) afirst step of preparing a semiconductor substrate; (b) a second step offorming a first ion implanting mask with a predetermined opening on asurface of the semiconductor substrate and forming the firstconductivity-type well by implanting first conductivity-type dopant intothe semiconductor substrate with the first ion implanting mask as amask; (c) a third step of forming, after removal of the first ionimplanting mask, a second ion implanting mask with a predeterminedopening on a surface of the semiconductor substrate and forming thefirst conductivity-type ON resistance lowering well so as to contact thefirst conductivity-type well by implanting first conductivity-typedopant with a higher concentration than the second step with the secondion implanting mask as a mask; (d) a fourth step of forming, afterremoval of the second ion implanting mask, a third ion implanting maskwith a predetermined opening on a surface of the semiconductor substrateand forming the second conductivity-type well so as to not contact thefirst conductivity-type ON resistance well by implanting secondconductivity-type dopant with the third ion implanting mask as a mask;(e) a fifth step of forming, after removal of the third ion implantingmask, a field oxide film with a predetermined opening in a surface ofthe semiconductor substrate, and forming the gate insulating film bythermal oxidization at the opening in the field oxide film; (f) a sixthstep of forming the gate electrode in a predetermined region on the gateinsulating film; and (g) a seventh step of forming the firstconductivity-type source region and the first conductivity-type drainregion by implanting first conductivity-type dopant with at least thegate electrode and the field oxide film as a mask.
 22. A method ofmanufacturing a lateral short-channel DMOS according to claim 21,wherein in the fourth step, a second conductivity-type diffused regionis formed in a floating state in a region of the first conductivity-typewell between the second conductivity-type well and the firstconductivity-type drain region so as to not contact the secondconductivity-type well.
 23. A method of manufacturing a lateralshort-channel DMOS according to claim 22, wherein in the fourth step,the second conductivity-type diffused region is formed so as to notcontact the first conductivity-type ON resistance lowering well.
 24. Amethod of manufacturing a lateral short-channel DMOS according to claim22, wherein in the fifth step, the field oxide film is formed so as toinclude a region from the second conductivity-type diffused region tothe first conductivity-type drain region.
 25. A semiconductor deviceincluding a lateral short-channel DMOS according to claim 1.